@article{TC2009+ECC,
 author = {Kim, Soontae},
 title = {Reducing Area Overhead for Error-Protecting Large {L2/L3} Caches},
 journal = {IEEE Trans. Comput.},
 volume = {58},
 number = {3},
 year = {2009},
 issn = {0018-9340},
 pages = {300--310},
 doi = {http://dx.doi.org/10.1109/TC.2008.174},
 publisher = {IEEE Computer Society},
 address = {Washington, DC, USA},
 }


@article{ISCA09+ECC,
 author = {Yoon, D. H. and Erez, M.},
 title = {Memory mapped {ECC}: low-cost error protection for last level caches},
 journal = {In Proceedings of ISCA},
 volume = {},
 number = {},
 year = {2009},
 issn = {0163-5964},
 pages = {116--127},
 doi = {http://doi.acm.org/10.1145/1555815.1555771},
 publisher = {ACM},
 address = {New York, NY, USA},
 }

@article{power4,
 author = {D.C. Bossen and J.M. Tendler and K. Reick},
 title = {POWER4 System Design for High Reliability},
 journal = {IEEE Micro},
 volume = {},
 number = {},
 year = {2002},
 issn = {},
 pages = {},
 doi = {},
 publisher = {},
 address = {},
 }


@article{arm,
 author = {R. Phelan},
 title = {Addressing Soft Errors in ARM Core-Based SoC},
 journal = {ARM},
 volume = {},
 number = {},
 year = {2003},
 issn = {},
 pages = {},
 doi = {},
 publisher = {},
 address = {},
 }

@article{itanium,
 author = {N. Quach},
 title =  {High Availability and Reliability in the Itanium Processor},
 journal = {IEEE Micro},
 volume = {},
 number = {},
 year = {2000},
 issn = {},
 pages = {},
 doi = {},
 publisher = {},
 address = {},
 }

@inproceedings{ISCA09+MSPRAM,
 author = {Lee, B. C. and Ipek, E. and Mutlu, O. and Burger, D.},
 title = {Architecting phase change memory as a scalable dram alternative},
 booktitle = {Proceedings of ISCA},
 year = {2009},
 isbn = {978-1-60558-526-0},
 pages = {2--13},
 location = {Austin, TX, USA},
 doi = {http://doi.acm.org/10.1145/1555754.1555758},
 publisher = {},
 address = {},
 }

@inproceedings{ISCA09+Yang,
 author = {Zhou, P. and Zhao, B. and Yang, J. and Zhang, Y.},
 title = {A durable and energy efficient main memory using phase change memory technology},
 booktitle = {Proceedings of ISCA},
 year = {2009},
 isbn = {978-1-60558-526-0},
 pages = {14--23},
 location = {Austin, TX, USA},
 doi = {http://doi.acm.org/10.1145/1555754.1555759},
 publisher = {},
 address = {},
 }

@inproceedings{ISCA09+xiaoxia,
 author = {Qureshi, M. K. and Srinivasan, V. and Rivers, J. A.},
 title = {Scalable high performance main memory system using phase-change memory technology},
 booktitle = {Proceedings of ISCA},
 year = {2009},
 isbn = {978-1-60558-526-0},
 pages = {24--33},
 location = {Austin, TX, USA},
 doi = {http://doi.acm.org/10.1145/1555754.1555760},
 publisher = {},
 address = {},
 }

@INPROCEEDINGS{HPCA09+Guangyu,
title={A novel architecture of the {3D} stacked {MRAM} {L2} cache for {CMPs}},
author={G. Sun and X. Dong and Y. Xie and J. Li and Y. Chen},
booktitle={Proceedings of HPCA},
year={2009},
month={},
volume={},
number={},
pages={239-249},
keywords={MRAM devices, SRAM chips, cache storage, memory architecture3D heterogeneous integrations, 3D stacked MRAM L2 cache, SRAM counterparts, conventional chip multiprocessors, magnetic random access memory, read-preemptive write buffer},
doi={10.1109/HPCA.2009.4798259},
ISSN={1530-0897}, }

@INPROCEEDINGS{jun+hpca09,
title={A low-radix and low-diameter {3D} interconnection network design},
author={Y. Xu and Y. Du and B. Zhao and X. Zhou and Y. Zhang and J. Yang},
booktitle={Proceedings of HPCA},
year={2009},
month={},
volume={},
number={},
pages={30-42},
keywords={digital arithmetic, logic design, multiprocessor interconnection networks, network routing, network topology, network-on-chip3D network-on-chip topology design, 3D stacking technology, chip multiprocessor, low radix router, low-diameter 3D interconnection network design, one-hop vertical communication design, small-to-medium sized clique network, sub-micron technology},
doi={10.1109/HPCA.2009.4798234},
ISSN={1530-0897}, }

@INPROCEEDINGS{SE+CAM,
title={{A Soft-Error Tolerant Content-Addressable Memory (CAM) Using An Error-Correcting-Match Scheme}},
author={Pagiamtzis, K. and Azizi, N. and Najm, F.N.},
booktitle={Proceedings of CICC},
year={2006},
month={Sept.},
volume={},
number={},
pages={301-304},
keywords={content-addressable storage, error correction codes, neutron effects, radiation hardening (electronics)Hamming distance, SRAM, alpha particle, bit upsets, error-correcting codes, error-correcting-match scheme, integrated circuits, modified matchline sensing, neutron hits, single-event upsets, soft-error tolerant content-addressable memory},
doi={10.1109/CICC.2006.320887},
ISSN={}, }

@INPROCEEDINGS{CAM1,
title={{A Dual-Supply 4GHz 13fJ/bit/search 6C4128b CAM in 65nm CMOS}},
author={Agarwal, A. and Hsu, S.K. and Kaul, H. and Anders, M.A. and Krishnamurthy, R.K.},
booktitle={Proceedings of ESSCIRC},
year={2006},
month={Sept. },
volume={},
number={},
pages={303-306},
keywords={CMOS memory circuits, content-addressable storage1.2 V, 13fJ/bit/search operation, 4 GHz, 65 nm, CMOS technology, content-addressable-memory, dual-supply CAM, full rail technique, global bitline accelerator},
doi={10.1109/ESSCIR.2006.307591},
ISSN={1930-8833}, }

@INPROCEEDINGS{CAM2,
title={{Design trend of energy-efficient CAMs}},
author={J. Wang and C. Wang and T. Chen},
booktitle={Proceedings of ISOCC},
year={2008},
month={Nov.},
volume={},
number={},
pages={I-21-I-24},
keywords={CMOS digital integrated circuits, content-addressable storage, integrated circuit designCMOS technology, application-specific designs, content addressable memory, energy-efficient CAM, match-line design, search-line design},
doi={10.1109/SOCDC.2008.4815565},
ISSN={}, }

@ARTICLE{CAM3,
title={{Content-addressable memory (CAM) circuits and architectures: a tutorial and survey}},
author={Pagiamtzis, K. and Sheikholeslami, A.},
journal={IEEE Journal of Solid-State Circuits},
year={2006},
month={March},
volume={41},
number={3},
pages={ 712-727},
keywords={ NAND circuits, NOR circuits, content-addressable storage, logic design, low-power electronics NAND cell, NOR cell, bank selection, content addressable memory circuits, high-speed table lookup, lookup-table function, low-power matchline sensing techniques, matchline pipelining, network routers, packet classification, packet forwarding, parallel active circuitry, searchline driving},
doi={10.1109/JSSC.2005.864128},
ISSN={0018-9200}, }

@ARTICLE{MRAM+CAM1,
title={Magnetic Content Addressable Memory},
author={W. Wang and Z. Jiang},
journal={Magnetics, IEEE Transactions on},
year={2007},
month={June },
volume={43},
number={6},
pages={2355-2357},
keywords={content-addressable storage, magnetic storage, magnetic structure, magnetic tunnelling, micromagneticsAnsoft Maxwell software, CAM bit, LLG micromagnetic simulations, Landau-Liftshitz-Gilbert micromagnetic simulations, MTJ CAM cell design, magnetic content addressable memory, magnetic field confinement, magnetic tunneling junction device, programmed spin orientations, programming current, programming magnetic field, thin top magnet electrode, tunneling junction resistance, vertical ring-shaped bottom magnet electrode},
doi={10.1109/TMAG.2007.893305},
ISSN={0018-9464}, }


@ARTICLE{MRAM+CAM2,
title={Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed},
author={W. Xu and T. Zhang and Y. Chen},
journal={VLSI, IEEE Transactions on},
year={2009},
month={ },
volume={},
number={},
pages={},
keywords={},
doi={},
ISSN={}, }
 
@INPROCEEDINGS{li+ASAP,
title={Managing multi-core soft-error reliability through utility-driven cross domain optimization},
author={W. Zhang and T. Li},
booktitle={Proceedings of ASAP},
year={2008},
month={},
volume={},
number={},
pages={132-137},
keywords={},
doi={},
ISSN={}, }


@INPROCEEDINGS{factor,
title={Factors that impact the critical charge of memory elements},
author={Heijmen, T. and Giot, D. and Roche, P.},
booktitle={Proceedings of IOLTS},
year={2006},
month={},
volume={},
number={},
pages={6 pp.-},
keywords={integrated circuit reliability, radiation effects, semiconductor device models, transistorsPMOS ON-current, back-end parasitics, current pulse width, current waveform, memory cell, memory elements critical charge, node capacitance, parameter variations, process variant, soft error rate estimation, supply voltage, temperature, transistor model parameters},
doi={10.1109/IOLTS.2006.35},
ISSN={}, }

@inproceedings{softarch,
 title = {SoftArch: An Architecture Level Tool for Modeling and Analyzing Soft Errors},
author={X. Li and S. V. Adve and P. Bose and J. A. Rivers},
 booktitle = {Proceedings of DSN},
 year = {2005},
 isbn = {0-7695-2282-3},
 pages = {496--505},
 doi = {http://dx.doi.org/10.1109/DSN.2005.88},
 publisher = {},
 address = {},
 }

@article{phaser,
 author = {Rivers, J. A. and Bose, P. and Kudva, P. and Wellman, J.-D. and Sanda, P. N. and {\em et al}},
 title = {Phaser: phased methodology for modeling the system-level effects of soft errors},
 journal = {IBM Journal of Research and Development},
 volume = {52},
 number = {3},
 year = {2008},
 issn = {0018-8646},
 pages = {293--306},
 publisher = {IBM Corp.},
 address = {Riverton, NJ, USA},
 }

@article{online,
 author = {Li, X. and Adve, S. V. and Bose, P. and Rivers, J. A.},
 title = {Online Estimation of Architectural Vulnerability Factor for Soft Errors},
 journal = {Proceedings of ISCA},
 volume = {},
 number = {},
 year = {2008},
 issn = {0163-5964},
 pages = {341--352},
 doi = {http://doi.acm.org/10.1145/1394608.1382150},
 publisher = {ACM},
 address = {New York, NY, USA},
 }

@inproceedings{shubu,
 author = {Mukherjee, S. S. and Weaver, C. and Emer, J. and Reinhardt, S. K. and Austin, T.},
 title = {A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor},
 booktitle = {Proceedings of MICRO},
 year = {2003},
 isbn = {0-7695-2043-X},
 pages = {29},
 publisher = {},
 address = {},
 }

@inproceedings{weaver,
 author = {Weaver, C. and Emer, J. and Mukherjee, S. S. and Reinhardt, S. K.},
 title = {Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor},
 booktitle = {Proceedings of ISCA},
 year = {2004},
 isbn = {0-7695-2143-6},
 pages = {264},
 location = {M\"{u}nchen, Germany},
 publisher = {},
 address = {},
 }

@inproceedings{hamming,
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 title = {Error Correcting and Error Detecting Codes},
 booktitle = {Bell System Technical Journal},
 year = {April, 1950},
 isbn = {},
 pages = { 29:14-160},
 location = {},
 publisher = {},
 address = {},
 }

@article{hsiao,
author = {Hsiao, M. Y.},
citeulike-article-id = {5054651},
journal = {IBM Journal of Research and Development},
keywords = {dram-error, edac, hardware-fault, reliability, single-event-upset, soft-error},
number = {4},
pages = {395--401},
posted-at = {2009-07-04 13:10:15},
priority = {0},
title = {A Class of Optimal Minimum Odd-weight-column SEC-DED Codes},
volume = {14},
year = {1970}
}

@article{29,
author = {Slayman, C.W.},
citeulike-article-id = {5054651},
journal = {Device and Materials Reliability, IEEE Transactions on},
keywords = {},
number = {},
pages = {397- 404},
posted-at = {},
priority = {},
title = {Cache and memory error detection, correction, and reduction techniques for terrestrial servers and workstations},
volume = {},
year = {Spet., 2005}
}

@article{3DUtah,
author = {Madan, N. and  L. Zhao  and  Muralimanohar, N. and  Udipi, A. and  Balasubramonian, R. and {\em et al}},
citeulike-article-id = {},
journal = {In Proceedings of HPCA},
keywords = {},
number = {},
pages = {262-274},
posted-at = {},
priority = {},
title = {Optimizing communication and capacity in a {3D} stacked reconfigurable cache hierarchy},
volume = {},
year = {2009}
}

@article{omp2001,
author = {www.spec.org},
citeulike-article-id = {5054651},
journal = {},
keywords = {},
number = {},
pages = {},
posted-at = {},
priority = {},
title = {},
volume = {},
year = {}
}


@inproceedings{parsec,
  author = {C. Bienia and S. Kumar and J. Pal Singh and K. Li},
  title = {The PARSEC Benchmark Suite: Characterization and Architectural Implications},
  booktitle = {Proceedings of PACT},
  year      = {2008},
  month     = {October}
}


@article{,
author = {},
citeulike-article-id = {5054651},
journal = {},
keywords = {},
number = {},
pages = {},
posted-at = {},
priority = {},
title = {},
volume = {},
year = {}
}

@article{,
author = {},
citeulike-article-id = {5054651},
journal = {},
keywords = {},
number = {},
pages = {},
posted-at = {},
priority = {},
title = {},
volume = {},
year = {}
}

@inproceedings{MICRO09+3DSE,
 author = {W. Zhang and T. Li},
 title = {Microarchitecture soft error vulnerability characterization and mitigation under {3D} integration technology},
 booktitle = {Proceedings of MICRO},
 year = {2008},
 isbn = {978-1-4244-2836-6},
 pages = {435--446},
 doi = {http://dx.doi.org/10.1109/MICRO.2008.4771811},
 publisher = {},
 address = {},
 }

@article{IBM:MRAM,
 author = {W. J. Gallagher and S. S. P. Parkin},
 title = {Development of the magnetic tunnel junction MRAM at IBM: From first
                  junctions to a 16-Mb MRAM demonstrator chip},
 journal = {IBM Journal of Research and Development},
 volume = {50},
 number = {1},
 year = {2006},
 issn = {0018-8646},
 pages = {5--23},
 publisher = {},
 address = {},
 }
